Fabrication of semiconductor devices or integrated circuits requires many complex steps. Heat treatment is an important step in the fabrication of semiconductor devices and is used to carry out a variety of processes such as thermal annealing and thermal oxidation, among many other processes.
As well known in the art, semiconductor devices are made of a number of conductive and insulating features on a semiconductor substrate. Devices such as gate electrodes comprised of a gate stack including layers of materials such as polysilicon, dielectric, and metals are commonly used. For semiconductor devices having a critical geometry requirement of less than 130 nm, the polysilicon layer may be strapped over the top by a metal silicide layer. However, it has been found that the circuit performance of such a device is limited due to resistance of the device to device interconnect lines. To reduce the resistance of these interconnect lines, it has been proposed in the industry to replace the metal silicide layer and to fabricate the interconnect lines of polysilicon strapped over the top by a barrier layer and then a metal layer which exhibits a lower resistance than the metal silicide layer, as illustrated in FIG. 1.
Plasma etch processing is typically used to define the gate device. The plasma etch step leaves a roughened edge on the polysilicon layer and produces plasma induced damage near the gate dielectric layer at the bottom of the polysilicon layer. Such damage may cause device failure or degraded performance. Methods have been developed in an attempt to minimize such failure or degraded performance. Methods have been developed in an attempt to minimize such damage, and have included an oxidation step to form a thin oxide layer of approximately 5 to 15 nm thick on the sidewall of the polysilicon layer to repair the plasma damage caused in the plasma step.
It has been found however, that during this oxidation step used to repair the plasma damage, the oxygen-rich environment exposes the metal layer to attack and the oxidant can destroy the metal layer. To address this problem, selective oxidation processes have been investigated.
In one prior art approach, selective oxidation of gate electrodes having polysilicon and tungsten metal structures has been performed in single wafer reactors using a catalytic reactor which reacts hydrogen and oxygen to form partial pressure of water vapor in the reactor ambient. Such an approach suffers from disadvantages however, such as high cost of the catalytic reactor and low throughput (less than approximately 10 wafers per hour achievable by such a single wafer system).
Batch furnace systems have long been employed to carry out annealing processes in the fabrication of semiconductor wafers. Many batch annealing processes are carried out in a hydrogen environment (hydrogen anneal). In most annealing processes, hydrogen is diluted with nitrogen, and safety features such gas ratio interlocks are used to control the hydrogen to concentrations below the explosive or flammability limit. However, for some process applications annealing in an atmosphere of up to 100% hydrogen is required. Systems of this type incorporate use of circuits that force a timed nitrogen purge of the reactor or tube prior to the flow of hydrogen gas, and an automated post purge of nitrogen applied upon the termination of the flow of hydrogen gas. While this approach is useful, improvements are needed. Accordingly, improved systems and methods for selectively oxidizing one material with respect to another in the fabrication of semiconductor devices is desired.